Size reduction of metal-oxide-semiconductor field-effect transistors (MOSFETs), including reduction of the gate length and gate oxide thickness, has enabled the continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. To further enhance transistor performance, MOSFET devices have been fabricated using strained channel regions located in portions of a semiconductor substrate. Strained channel regions allow enhanced carrier mobility to be realized, thereby resulting in increased performance when used for n-channel (NMOSFET) or for p-channel (PMOSFET) devices. Generally, it is desirable to induce a tensile strain in the n-channel of an NMOSFET transistor in the source-to-drain direction to increase electron mobility and to induce a compressive strain in the p-channel of a PMOSFET transistor in the source-to-drain direction to increase hole mobility. There are several existing approaches of introducing strain in the transistor channel region.
In another approach, strain in the channel is introduced by creating a recess in the substrate in the source/drain regions. For example, a PMOS device may have a stress-inducing layer such as SiGe is epitaxially grown within the recessed regions extending above a surface of the substrate, thereby introducing strain in the channel. The amount of stress may be increased by increasing the Ge concentration during the growth process. Increasing the Ge concentration in the recessed area, however, creates process challenges. For example, increasing the Ge concentration during the epitaxial growth results in a higher density of dislocations and defects in the SiGe layer. Degraded selectivity and deposition process windows are also of concern.
In combination with the stress-inducing layer in the recesses in the source/drain regions, contact etch stop layers have also been used. In this approach, contact etch stop layers are formed over the transistor such that the etch stop layer exerts stress in the channel region of the underlying transistor. The contact etch stop layer may be different for NMOS and PMOS devices, which is referred to as a Dual Contact Etch Stop Layer (D-CESL).
The raised source/drain regions, however, buffers the effect of the contact etch stop layers and degrading the stress effect of the contact etch stop layer. Accordingly, there is need for a method to induce strain in the channel region such that the performance characteristics of transistors are enhanced.